ADP5022
Rev. C | Page 18 of 28
Enable/Shutdown
The bucks start operation with soft start when the EN1 or EN2
pin is toggled from logic low to logic high. Pulling the EN1 or
EN2 pin low disables that channel.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possi-
bility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a drop in input voltage or with an increase in load current,
the buck may reach a limit where, even with the PFET switch
on 100% of the time, the output voltage drops below the desired
output voltage. At this limit, the buck transitions to a mode
where the PFET switch stays on 100% of the time. When the
input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage. This is particularly
useful in battery-powered applications to achieve the longest
operation time by taking full advantage of the whole battery
voltage range. Maintaining regulation is dependent on the input
voltage, load current, and output voltage. This can be calculated
from the following equation:
V
IN(MIN)
= V
OUT(MAX)
+ I
LOAD(MAX)
?(R
DS(on)MAX
+ R
L
)
where:
V
OUT(MAX) is the nominal output voltage plus the maximum
tolerance.
ILOAD(MAX) is the maximum load current plus inductor ripple
current.
R
DS(on)MAX
is the maximum P-channel switch R
DS(on)
.
R
L
is the DC resistance of the inductor.
LDO SECTION
The LDO is a low quiescent current, low dropout linear
regulator and provides up to 150 mA of output current.
Drawing a low 30 糀 quiescent current (typical) at full load
makes the LDO ideal for battery-operated portable equipment.
The LDO operates with an input voltage of 2.3 V to 5.5 V.
It also provides high power supply rejection ratio (PSRR), low
output noise, and excellent line and load transient response
with just a small 1 糉 ceramic input and output capacitor.
Internally, the LDO consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con-
trolled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
reducing the current flowing to the output.
LDO Undervoltage Lockout
The ADP5022 integrates an undervoltage lockout function
on the VIN3 input voltage, which ensures that the LDO
output drive is disabled whenever VIN3 is below a threshold
of approximately 2.0 V. Where the ADP5022 is configured to
supply VIN3 from either VOUT1 or VOUT2, this ensures that
the LDO powers up safely in this cascaded configuration.
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